Instruction set

This page defines the instruction set of B32P4, the CPU that runs in the FPGC. The instruction encoding is almost identical to B32P3, as B32P4 focuses mostly on performance and efficiency improvements instead of functional changes.

Overview

• 32-bit RISC, with 16 registers of 32 bits. r0 always reads as 0.
• Fixed-length 32-bit instructions, with the opcode always in the leftmost 4 bits.
• Byte-addressed, little-endian memory. Loads and writes can be 8, 16 or 32 bits wide.
• A hardware stack of 256 words for push and pop, separate from memory. Primarily for quick register backups.
• Hardware interrupts, taken only at jumps and branches to simplify the CPU pipeline.
• No security features. Since the goal is to be a personal hobby CPU where I am the only user, adding security features only adds unnecessary complexity.
• No floating point. To keep complexity down, decimal arithmetic is done using Q16.16 fixed-point format, just like the Sony PS1 did.
• Error register. (new feature in B32P4) Illegal instructions and accesses set a flag in the error register.

Notation

All arithmetic wraps around at 32 bits unless stated otherwise.

Registers

Instruction encoding

Every instruction is one 32-bit word. Bits marked x are unused in hardware.

         |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
----------------------------------------------------------------------------------------------------------
 HALT      1  1  1  1| 1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1
 READ      1  1  1  0||----------------16 BIT CONSTANT---------------||--A REG---||-RD SUBOP-||--D REG---|
 WRITE     1  1  0  1||----------------16 BIT CONSTANT---------------||--A REG---||--B REG---||-WR SUBOP|
 INTID     1  1  0  0| x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x |--D REG---|
 PUSH      1  0  1  1| x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x |--B REG---| x  x  x  x
 POP       1  0  1  0| x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x |--D REG---|
 JUMP      1  0  0  1||--------------------------------27 BIT CONSTANT--------------------------------||O|
 JUMPR     1  0  0  0||----------------16 BIT CONSTANT---------------| x  x  x  x |--B REG---| x  x  x |O|
 CCACHE    0  1  1  1| x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x
 CCACHED   0  1  1  1| x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  1
 BRANCH    0  1  1  0||----------------16 BIT CONSTANT---------------||--A REG---||--B REG---||-OPCODE||S|
 SAVPC     0  1  0  1| x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x |--D REG---|
 RETI      0  1  0  0| x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x  x
 ARITHMC   0  0  1  1||--OPCODE--||----------------16 BIT CONSTANT---------------||--A REG---||--D REG---|
 ARITHM    0  0  1  0||--OPCODE--| x  x  x  x  x  x  x  x  x  x  x  x |--A REG---||--B REG---||--D REG---|
 ARITHC    0  0  0  1||--OPCODE--||----------------16 BIT CONSTANT---------------||--A REG---||--D REG---|
 ARITH     0  0  0  0||--OPCODE--| x  x  x  x  x  x  x  x  x  x  x  x |--A REG---||--B REG---||--D REG---|

ALU instructions

ARITH and ARITHC use the single-cycle ALU. The operation is D = A op B, where the second operand B is:

• ARITH: register B
• ARITHC: sext(c16), except load and loadhi, which use zext(c16)

• Shifts use only the low 5 bits of B, so a shift by 32 is a shift by 0.

• Constants for sltu are sign-extended too: sltu r1 -1 r2 compares with 0xFFFFFFFF.

• Loading a 32-bit constant takes two instructions:

  1. load c16 D sets D = zext(c16).
  2. loadhi c16 D, assembled with A = D, sets the upper half and keeps the lower half.

  The assembler’s load32 and addr2reg expand into these two instructions.

Multiply and divide instructions

ARITHM and ARITHMC have the same form as ARITH and ARITHC: B is register B, or sext(c16). These take multiple cycles to complete (stalls the CPU).

Defined edge cases:

Memory instructions

READ and WRITE access memory at the byte address A + sext(c16).

• Little-endian: the byte at address n is bits [7:0] of the word at n & ~3.
• Word accesses must be at a multiple of 4, halfword accesses at a multiple of 2.

Hardware stack

The stack is 256 words of on-chip memory, separate from the address space. It’s meant for saving registers in functions and interrupt handlers.

• The SP can be read (not written) by reading a specific CPU-internal I/O register, which gives software (such as a context switch) access to SP.
• The SP wraps around on overflow and underflow.

Control flow instructions

• All targets are byte addresses and must be multiples of 4.
• The range of absolute jump is 0 to 128 MiB which covers SDRAM. Higher jumps should use jumpo or jumpr.
• A branch reaches ±32 KiB from itself, as the argument is an offset from the current PC. Can be combined with a jump instruction for larger jumps.
• HALT keeps the CPU on one instruction until an interrupt is taken. Implemented by jumping to the current address.

Branch conditions

SAVPC

savpc D sets D = PC, the address of the savpc itself. Together with an add, this can be used to create a return address for function jumps.

Interrupts

The CPU has several interrupt inputs, with IDs 1 starting from 1 upwards. ID 1 has the highest priority.

Pending interrupts:

• A rising edge on an input makes that interrupt pending.
• A pending interrupt stays pending until it’s taken, one at a time, in priority order.

When an interrupt is taken, all of these must hold:

• interrupts are enabled
• an interrupt is pending
• the CPU is about to execute a jump, jumpr, taken branch or halt
• that instruction is in SDRAM, so ROM code is never interrupted

This simplifies the implementation: the interrupt is taken instead of that control-flow instruction.

1. pc_backup is set to the address of the control-flow instruction.
2. Interrupts are disabled.
3. Execution continues at address 0x4, the interrupt vector.

The handler reads the ID with INTID, handles the interrupt and ends with RETI.

After RETI, the interrupted control-flow instruction executes as if nothing happened.

Other rules:

• No nesting: an interrupt that arrives during the handler stays pending until after RETI.
• Interrupts are enabled after reset. There are no instructions to enable or disable them.
• Reading pc_backup: the handler can read and write it via a CPU-internal register, for example to switch tasks.

Cache instructions

SDRAM is accessed through an instruction cache (L1I) and a data cache (L1D). There are two instructions to invalidate the caches, which is needed for loading code into SDRAM, or for DMA operations.

Memory map

The CPU’s view of the 32-bit address space. Other addresses ignore writes and return 0 for reads.

Only SDRAM and ROM can hold executable code.

CPU-internal I/O registers

Error register

ERR_STATUS records illegal events, to help debugging:

• The flags are sticky: each flag stays set until software clears it by writing ERR_STATUS.
• The first event is recorded in detail: its kind (bits [10:8]) and its instruction address (ERR_PC). Later events only set their flag.

All other bits read as 0.

• If one instruction causes two events, both flags are set, and the lower kind number counts as the first.
• Instructions that never execute don’t set flags.

Currently no interrupt is attached to this, I might add that later.