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FPGC Wiki

Architecture

bartpleiter/FPGC

FPGC Wiki

bartpleiter/FPGC

FPGC
System overview
System overview
- Specifications
- Architecture Architecture
  Table of contents
  - System level architecture
Hardware
Hardware
- FPGA
- CPU (B32P2)
  CPU (B32P2)
  - CPU (B32P2)
  - Architecture diagrams
  - Modules
    Modules
    
    ALU
    
    Address decoder
    
    Branch and Jump Unit
    
    Control Unit
    
    Instruction Decoder
    
    Multi-Cycle ALU
    
    Register Bank
    
    Pipeline Register (Regr)
    
    Stack
  - ISA
  - Cache
- GPU (FSX2)
  GPU (FSX2)
  - GPU (FSX2)
- IO
  IO
  - I/O
- Memory
  Memory
  - MIG 7
  - Memory map
- PCB
  PCB
  - PCB
Software
Software
- Assembler
  Assembler
  - Assembler
- Bootloader
  Bootloader
  - Bootloader
- C compiler
  C compiler
  - C Compiler
- Libraries
  Libraries
  - Libraries
- OS
  OS
  - OS (BDOS)
- Programs
  Programs
  - Programs
Development
Development
- Simulation
- Build scripts
  Build scripts
  - Programmer
  - Python environment
- Vivado
  Vivado
  - Vivado
Physical design
Physical design
- Case
  Case
  - Case
- Monitor
  Monitor
  - Monitor
Getting started
Getting started
- FPGA Simulation
- Hardware

Architecture

Note

For other architectures like software/OS level or component specific level, see relevant pages.

System level architecture

FPGC_arch