Vivado

TODO Write the following:

• Vivado version to use
• All verilog files are placed in the vivado project, no different source files for use with iverilog to prevent duplication
  • Uses macros to include or exclude code to be used in Vivado or iverilog
• How to build for the FPGA
• The hack needed to allow this specific version of the SPI flash chip to work
• The IP used (PLLs and MIG 7)